1. Field of the Invention
The present invention generally relates to a semiconductor integrated circuit. More particularly, the invention relates to a semiconductor integrated circuit having semiconductor packages of CSP (chip size package or chip scale package) structure for mounting integrated circuit chips on both sides of a substrate.
2. Description of the Background Art
A CSP structure semiconductor package capable of significantly enhancing packaging density is disclosed illustratively in Japanese Patent Laid-open No. Hei 9-107048. FIG. 12 is a perspective view corresponding to a CSP shown in FIG. 31 of the cited publication. In FIG. 12, reference numeral 9 stands for a CSP in which electrode pads 3 are connected to electrode bumps 1 via frame wiring 2 that forms connection wiring inside the package. The package is mounted on a substrate, not shown, by melting the electrode bumps 1 that serve as external connection electrodes of the CSP 9.
The electrode pads 3 are capable of being formed at anywhere on an integrated circuit chip 8. However, the CSP 9 is required to ease stress applied to integrated circuit elements under electrode bumps 1 when the bumps 1 are being formed or the CSP 9 is getting mounted on the substrate. Thus, there exist a number of constraints on the design of connection wiring for the electrode bumps 1 and of layout positions of the electrode pads 3.
Mounting CSPs on both sides of a substrate involves preparing a pair of CSPs (called the CSP mirror pair hereunder) made of an ordinary package (also called the front side package or reverse mirror package hereunder) to be mounted on the top, i.e., the front side of the substrate, and a back side package (also called the mirror package hereunder) to be attached to the back side of the substrate. Referring to FIG. 13, a CSP mirror pair is illustratively constituted by a CSP 91 and a CSP 92. One of the paired CSPs 91 and 92 serves as the front side CSP and the other as the back side CSP mounted on the respective sides of a module substrate.
The CSP mirror pair is characterized in that a plurality of electrode bumps formed on the principal planes of the front side CSP and back side CSP are arranged symmetrically with respect to the substrate. For example, looking from above the principal plane of the CSP mirror pair in FIG. 13, it is noticed that rows of electrode bumps 1A through 1E and 1N through 1S are located symmetrically between the CSP 91 and CSP 92. The CSP mirror pair may be mounted on both sides of a substrate selected from among diverse kinds of substrates including the module substrate. The front side and back side CSPs are interchangeable as long as they are mounted in pair on the two sides of the substrate.
A majority of conventional CSP mirror pairs are exemplified, as shown in a plane view of FIG. 14, by a CSP mirror pair 100 each package having a row of electrode pads and two rows of electrode bumps. The arrangement has been favored because there are relatively few constraints on the layout of the electrode bumps and because of the ease of installing connection wiring within the packages.
In FIG. 14, a front side chip 103 and a back side chip 104 are formed under the principal planes of a front side package 101 and a back side package 102 respectively. This is a typical CSP structure in which a plurality of electrode pads 3A through 3S are aligned in a row in the middle of the principal plane of each chip. In the structure seen in FIG. 14, the electrode pads 3A through 3E and 3N through 3S are apportioned right and left to be connected to frame wires 2A through 2E and 2N through 2S inside each package. The frame wires are in turn connected to the right- and left-hand side rows of the electrode bumps 1A through 1E and 1N through 1S serving as external connection electrodes of the CSP. The layout permits easy installation of connection wiring.
In FIG. 14, the chips 103 and 104, electrode pads 1 and frame wires 2 are indicated by dash-dot lines and solid lines although they are not actually seen from the principal planes of the packages 101 and 102. The same convention applies to the figures to be referred to hereunder.
High degrees of circuit integration and concentration as well as enhanced functions afforded by memory-logic hybrid circuitry have boosted the capacity of, and the number of pins on, CSPs. Such trends are liable to entail increases in packaging area with electrode pads crowded out of packages because the CSP structure has its electrode pads aligned in a row in the middle of the principal plane of each chip. Reductions in packaging area have failed to keep up with recent years"" particularly pronounced advances in miniaturization of circuits inside chips.
The present invention has been conceived to solve the previously-mentioned problems, and a general object of the present invention is to provide a novel and useful semiconductor integrated circuit.
A more specific object of the present invention is to provide CSPs small in size and fit to be mounted on both sides of a substrate.
It is a second object of the present invention to provide mirror CSPs fit to be mounted on both sides of a substrate, the CSPs accommodating chips having electrode pads and integrated circuits in the same positions.
It is a third object of the present invention to provide mirror CSPs fit to be mounted on both sides of a substrate, the CSPs accommodating chips having integrated circuits in the same positions.
It is a fourth object of the present invention to provide a small, high-density packaging assembly comprising a pair of small mirror CSPs mounted on both sides of a substrate.
The above objects of the present invention are achieved by a semiconductor integrated circuit including a pair of semiconductor packages. The semiconductor integrated circuit includes a pair of chips provided in the semiconductor packages, respectively. There are provided a plurality of integrated circuits in each of the chips so as to be disposed in a plurality of rows and in a plurality of stages. Each of the integrated circuits sends and receives signals. A plurality of electrode pads are provided on a principal plane of the chip so as to be disposed in a plurality of rows and in a plurality of stages. Each of the electrode pads is connected to the integrated circuits. A plurality of electrode bumps are provided on a surface of each of the semiconductor packages so as to be connected to the electrode pads to form external electrodes for the integrated circuits. One of the pair of semiconductor packages is in a first state in which the electrode bumps are placed on predetermined positions while the other of the pair of semiconductor packages is in a second state in which the electrode bumps are flipped from corresponding positions in the first state. The integrated circuits and the electrode bumps are interconnected differently between the first state and the second state, in such a manner that, when viewing from the principal plane, in a row J and a stage K of the pair of chips are all located identical integrated circuits and that the electrode bumps connected to the integrated circuits located in the row J and the stage K are all located symmetrically with respect to one another.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.